The present invention relates to techniques for testing programmable circuits, and more particularly, to techniques for isolating failed routing resources on a programmable integrated circuit.
Programmable integrated circuits include logic elements, memory, and conductors that are programmably connected in an interconnect structure. The logic elements and the connections to the conductors can be programmed according a number of different designs.
After a programmable circuit is manufactured, the logic elements, memory, and programmable connections in the interconnect structure are tested to ensure that they are operating properly. Tests are performed to detect the presence of manufacturing detects in the interconnect routing resources.
Locating failing routing resources is done manually. Upon encountering a low yielding lot, an engineer analyzes the testing logs to determine failing test patterns and nodes. The engineer then collects routing resources related to the failing nodes on each test pattern. From the collection, the engineer identifies the routing resources that most likely contain a defect. Then, the engineer creates test patterns to verify the failed routing resources and where the fault occurred. All this is done before submitting a sample for physical analysis. Physical analysis determines what process step caused the fault. Because most of these steps are performed manually, they can be very time consuming and are not cost effective.
Therefore, it would be desirable to provide techniques for testing programmable circuits to isolate failed routing resources that reduce the time spent by engineers to perform the tests.